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Introduction

IBM Research takes responsibility for technology and its role in society. Working in IBM Research means you'll join a team who invent what's next in computing, always choosing the big, urgent and mind-bending work that endures and shapes generations. Our passion for discovery, and excitement for defining the future of tech, is what builds our strong culture around solving problems for clients and seeing the real world impact that you can make.

IBM's product and technology landscape includes Research, Software, and Infrastructure. Entering this domain positions you at the heart of IBM, where growth and innovation thrive.

Your role and responsibilities

IBM Semiconductor Research & Development at Albany Nanotech are currently seeking a skilled engineer in the area of test structure design enablement and design infrastructure development for the world's cutting edge semiconductor technologies. We are seeking qualified and motivated candidates for a position as Design Automation and Infrastructure Engineer.

The hired candidate will have experience with electrical engineering, and/or computer engineering, and/or semiconductor physics. The candidate must understand the principles of semiconductor physics, physical layout design, and design infrastructures development. The candidate will work closely with process development engineers, device engineers, reliability engineers, health of line engineers and layout technicians to create layout automation that meets the intent of the above engineers. The hired candidate must also possess strong analytical and design-of-experiment knowledge, excellent written and verbal communication skills, and the ability to articulate difficult concepts to an audience with diverse technical backgrounds.

The job responsibilities include developing test structure layouts using design automation by SKILL coding, using industry standard (EDA) tools including the Cadence Virtuoso Design Environment, and design infrastructure development with SKILL/Python/Perl. The position involves developing parametrized cells (p-cells) for use in design automation. Engineers in this position interpret design rules and macro specifications, collaborating with engineers from other functional areas to achieve the desired structure while ensuring that designed layouts pass Design Rule Checks (DRC). Specified layouts will be primarily test structures rather than working circuitry. Close and frequent cooperation with development engineers from interdisciplinary teams will be required for this dynamic team environment. More experienced individuals will participate in coordination of projects, teams, and/or infrastructure development.

Required education

Bachelor's Degree

Preferred education

Master's Degree

Required technical and professional expertise

• Bachelor or above Degree in Electrical Engineering, Computer Engineering, Physics Engineering or related field with experience in VLSI chip development or semiconductor technology
• Experience using the Cadence Virtuoso layout design tool, at least 3 years
• Experience with Cadence SKILL programming language or related languages (Python and/or Perl, etc), at least 3 years
• Experience with Cadence design infrastructure development (SKILL, Python or Perl scripting)
• Familiarity with layout verification tools from Cadence Pegasus, Synopsys ICV, or Siemens Calibre, including design rule checking (DRC) with 3+ years of relevant experience
• Strong understanding of physical layout and technology ground rules
• Strong understanding of Linux environments and shell scripting with a minimum of 2+ years of experience
• Ability to debug errors and solve problems in a team environment
• Fluent English (both verbal and written) and strong communication skills

Preferred technical and professional experience

• Strong experience using the Cadence Virtuoso layout design tool, at least 5 years
• Experience with Cadence SKILL programming language for pcell development & design automation, at least 3 years
• Strong experience with Cadence design automation infrastructure development
• Experience with advanced sub-micron semiconductor technology nodes
• Experienced user of Synopsys ICV DRC checking tool
• Experience with version control systems such as Git and familiarity with collaborative software development workflows (e.g., GitHub, GitLab, or Bitbucket)